1. Field of the Invention
The present invention generally relates to methods for forming a barrier layer on a substrate. More specifically, the present invention provides methods for forming a barrier layer for barrier applications in a metal interconnect structure.
2. Description of the Related Art
Interconnect structures of integrated circuits and semiconductor devices are typically fabricated by forming a series of dielectric layers and conductive layers in order to create a three dimensional network of conductive layers separated by dielectric material. The interconnect structure may be fabricated using, for example, a damascene structure in which a dielectric layer such as a low-k dielectric layer is formed atop one or more conductive plugs or sub-layers. In order to form an electrical connection to the conductive sub-layers, the dielectric layer is patterned and etched to define via openings therethrough. Formation of the openings within the dielectric layer exposes a portion of the conductive layer. Therefore, reliable formation of these interconnect features is an important factor in ensuring the quality, performance and reliability of devices formed on individual substrates and in each die.
The market for integrated circuits and semiconductor devices continually requires faster circuitry and greater circuit density, e.g., including millions of components on a single chip. As a result, the dimensions of the integrated circuit components shrink, and the choice of materials used to fabricate such components becomes increasingly important. For example, low resistivity metal interconnects, such as copper and aluminum, that provide conductive paths between the components on the integrated circuits, now require low dielectric constant layers, e.g., having a dielectric constant≦4, between the metal interconnects to provide insulating inter-metal layers that reduce capacitive coupling between adjacent metal lines, thereby enabling reliable performance at small line widths.
Interconnect structure fabrication may be achieved by a variety of techniques. A typical method for forming layers for interconnect structures includes physical vapor deposition of a barrier layer over a feature, such as a trench or a via, followed by physical vapor deposition of a metal layer on the barrier layer to fill the feature. Finally, after the deposited material layers, including the metal and the dielectric layers, are formed on the substrate, a planarization or an etching process is performed to define a conductive interconnect feature with desired dimension on the substrate.
Problems encountered during metal interconnect manufacturing processes include metal diffusion and metal layer peeling and voids. A non-conformal or non-uniform barrier layer may prevent the to-be-deposited metal layer from continuously and uniformly depositing on the barrier layer, thereby forming voids and defects in the interconnect structure and eventually leading to device failure. Metal atoms from the metal layers may diffuse into the adjacent dielectric layers during subsequent deposition and/or anneal processes, thereby deteriorating the electrical property of the devices. Accordingly, a conformal and robust barrier layer becomes increasingly important to prevent the metal atoms from diffusing into adjacent dielectric layers. Moreover, it is desirable for a barrier layer to have a high wettability to the metal layer to be deposited thereon to promote good adhesion between the barrier and metal layers, which prevents the metal layer from peeling and flaking.
Therefore, there is a need in the art for an improved barrier layer suitable for use in an interconnect structure.